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Disambiguation of "Hanumolu, Pavan Kumar"

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A TDC-less 7mW 2.5Gb/s digital CDR with linear loop dynamics and offset-free data recovery.

, , , and . ISSCC, page 440-442. IEEE, (2011)

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Pavan Kumar

Pavan Kumar

Pavan Kumar Penumakala

Pavan Kumar Pendli

Pavan Kumar Pamarthi

 

Other publications of authors with the same name

An 11mW 100MHz 16X-OSR 64dB-SNDR hybrid CT/DT ΔΣ ADC with relaxed DEM timing., , , , , , , and . CICC, page 171-174. IEEE, (2009)A 0.5-to-2.5GHz supply-regulated PLL with noise sensitivity of -28dB., , and . CICC, page 443-446. IEEE, (2008)Area efficient phase calibration of a 1.6 GHz multiphase DLL., , and . CICC, page 1-4. IEEE, (2011)A 77dB SNDR, 4MHz MASH ΔΣ modulator with a second-stage multi-rate VCO-based quantizer., , , , and . CICC, page 1-4. IEEE, (2011)Digital clock and data recovery circuit design: Challenges and tradeoffs., , and . CICC, page 1-8. IEEE, (2011)A 0.7V time-based inductor for fully integrated low bandwidth filter applications., , , , , , and . CICC, page 1-4. IEEE, (2017)23.1 A 16Mb/s-to-8Gb/s 14.1-to-5.9pJ/b source synchronous transceiver using DVFS and rapid on/off in 65nm CMOS., , , , , , , , , and . ISSCC, page 398-399. IEEE, (2016)A 1.5GHz 1.35mW -112dBc/Hz in-band noise digital phase-locked loop with 50fs/mV supply-noise sensitivity., , , and . VLSIC, page 188-189. IEEE, (2012)A 2.8mW/Gb/s 14Gb/s serial link transceiver in 65nm CMOS., , , , , , , , and . VLSIC, page 352-. IEEE, (2015)10.3 A 94.2%-peak-efficiency 1.53A direct-battery-hook-up hybrid Dickson switched-capacitor DC-DC converter with wide continuous conversion ratio in 65nm CMOS., , , , and . ISSCC, page 182-183. IEEE, (2017)