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Disambiguation of "Sciuto, Donatella"

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Application of a Testing Framework to VHDL Descriptions at Different Abstraction Levels.

, , , , , and . ICCD, page 654-658. IEEE Computer Society, (1997)

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Donatella Cesare

Donatella Cesare

Donatella Germanese

Donatella Giovannini

Donatella Fiala

 

Other publications of authors with the same name

Combining hardware reconfiguration and adaptive computation for a novel SoC design methodology., , , and . FPT, page 293-296. IEEE, (2006)A Power-Efficient Methodology for Mapping Applications on Multi-Processor, System-on-Chip Architectures., , and . VLSI-SoC (Selected Papers), volume 249 of IFIP, page 177-196. Springer, (2006)A light-weight Network-on-Chip architecture for dynamically reconfigurable systems., , , and . ICSAMOS, page 49-56. IEEE, (2008)An adaptive genetic algorithm for dynamically reconfigurable modules allocation., , , and . VLSI-SoC, page 128-133. IEEE, (2007)A Functional Approach to Delay Faults Test Generation for Sequential Circuits., , and . EDAC-ETC-EUROASIC, page 51-57. IEEE Computer Society, (1994)Automatic Parallelization of Sequential Specifications for Symmetric MPSoCs., , , , , and . IESS, volume 231 of IFIP Advances in Information and Communication Technology, page 179-192. Springer, (2007)Internal and External Bitstream Relocation for Partial Dynamic Reconfiguration., , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 17 (11): 1650-1654 (2009)Mine with it or sell it: the superhashing power dilemma., , , and . SIGMETRICS Perform. Evaluation Rev., 46 (3): 127-130 (2018)HW/SW Co-design of Embedded Systems., and . Ada-Europe, volume 1622 of Lecture Notes in Computer Science, page 344-355. Springer, (1999)TaBit: A framework for task graph to bitstream generation., , , , , and . ICSAMOS, page 201-208. IEEE, (2012)