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Disambiguation of "Young, Evangeline F. Y."

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Layout Hotspot Detection With Feature Tensor Generation and Deep Biased Learning.

, , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 38 (6): 1175-1187 (2019)

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Grady Leon Young

Christopher Young

Charlotte Young

Hans Peter Young

Mark Young

 

Other publications of authors with the same name

Temporal logic replication for dynamically reconfigurable FPGA partitioning., and . ISPD, page 190-195. ACM, (2002)Layout Hotspot Detection With Feature Tensor Generation and Deep Biased Learning., , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 38 (6): 1175-1187 (2019)Temporal logic replication for dynamically reconfigurable FPGA partitioning., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 22 (7): 952-959 (2003)Fixed-Parameter Tractable Algorithms for Optimal Layout Decomposition and Beyond., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 38 (9): 1731-1743 (2019)Twin binary sequences: a nonredundant representation for general nonslicing floorplan., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 22 (4): 457-469 (2003)Simultaneous Reconnection Surgery Technique of Routing With Machine Learning-Based Acceleration., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 39 (6): 1245-1257 (2020)CUGR: Detailed-Routability-Driven 3D Global Routing with Probabilistic Resource Model., , , and . DAC, page 1-6. IEEE, (2020)Clustering based acyclic multi-way partitioning., , and . ACM Great Lakes Symposium on VLSI, page 203-206. ACM, (2003)Exploring Rule-Free Layout Decomposition via Deep Reinforcement Learning., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 42 (9): 3067-3077 (September 2023)Lagrangian Relaxation-Based Time-Division Multiplexing Optimization for Multi-FPGA Systems., and . ICCAD, page 1-8. ACM, (2019)