From post

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed.

 

Другие публикации лиц с тем же именем

Buffer delay change in the presence of power and ground noise., , и . IEEE Trans. Very Large Scale Integr. Syst., 11 (3): 461-473 (2003)Minimal Delay Interconnect Design Using Alphabetic Trees., и . DAC, стр. 392-396. ACM Press, (1994)System-Level Floorplan-Aware Analysis of Integrated CPU-GPUs., и . DAC, стр. 137:1-137:6. ACM, (2014)Delay and Area Optimization in Standard-Cell Design., , и . DAC, стр. 349-352. IEEE Computer Society Press, (1990)Clock network sizing via sequential linear programming with time-domain analysis., и . ISPD, стр. 182-189. ACM, (2004)Pre-layout wire length and congestion estimation., и . DAC, стр. 582-587. ACM, (2004)Buffer sizing for clock power minimization subject to general skew constraints., и . DAC, стр. 159-164. ACM, (2004)Aggressor alignment for worst-case crosstalk noise., и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 20 (5): 612-621 (2001)The crossing distribution problem IC layout., и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 14 (4): 423-433 (1995)A new reasoning scheme for efficient redundancy addition and removal., , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 22 (7): 945-951 (2003)