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Disambiguation of "Zhang, Bonan"

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A 256-kb Fully Row/Column-parallel 22nm MRAM In-Memory-Computing Macro with Differential Readout for Robust Parallelization and Scale-up.

, , and . ESSCIRC, page 21-24. IEEE, (2023)

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Karin Bonan

Marc Bonanni

Johannes Bonanati

Arno Bonanni

Andrea Bonanni

 

Other publications of authors with the same name

A 256-kb Fully Row/Column-parallel 22nm MRAM In-Memory-Computing Macro with Differential Readout for Robust Parallelization and Scale-up., , and . ESSCIRC, page 21-24. IEEE, (2023)A 22nm 128-kb MRAM Row/Column-Parallel In-Memory Computing Macro with Memory-Resistance Boosting and Multi-Column ADC Readout., , and . VLSI Technology and Circuits, page 268-269. IEEE, (2022)Statistical computing framework and demonstration for in-memory computing systems., , and . DAC, page 979-984. ACM, (2022)A Maximally Row-Parallel MRAM In-Memory-Computing Macro Addressing Readout Circuit Sensitivity and Area., , , and . ESSCIRC, page 75-78. IEEE, (2021)Stochastic Data-driven Hardware Resilience to Efficiently Train Inference Models for Stochastic Hardware Implementations., , and . ICASSP, page 1388-1392. IEEE, (2019)A Practical Botnet Traffic Detection System Using GNN., , , , and . CSS, volume 13172 of Lecture Notes in Computer Science, page 66-78. Springer, (2021)Compute SNR-boosted 22 nm MRAM-based In-memory Computing Macro using Statistical Error Compensation., , , , , , , and . ESSCIRC, page 25-28. IEEE, (2023)Neural Network Training With Stochastic Hardware Models and Software Abstractions., , and . IEEE Trans. Circuits Syst. I Regul. Pap., 68 (4): 1532-1542 (2021)