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Disambiguation of "Huang, Ru"

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Khronos: Fusing Memory Access for Improved Hardware RTL Simulation.

, , , , and . MICRO, page 180-193. ACM, (2023)

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Ru-Jin Huang

Ru Zhang

Ru Xie

Ru Hao

Tomasz Ru

 

Other publications of authors with the same name

Probabilistic Compute-in-Memory Design for Efficient Markov Chain Monte Carlo Sampling., , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 71 (2): 703-716 (February 2024)TD-SRAM: Time-Domain-Based In-Memory Computing Macro for Binary Neural Networks., , , , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 68 (8): 3377-3387 (2021)Time Complexity of In-Memory Matrix-Vector Multiplication., and . IEEE Trans. Circuits Syst. II Express Briefs, 68 (8): 2785-2789 (2021)Layout dependent BTI and HCI degradation in nano CMOS technology: A new time-dependent LDE and impacts on circuit at end of life., , and . ICICDT, page 1-3. IEEE, (2016)Benchmarking TFET from a circuit level perspective: Applications and guideline., , , , , , , and . ISCAS, page 1-4. IEEE, (2017)Recursive integral method with Cayley transformation., , and . Numerical Lin. Alg. with Applic., (2018)New-Generation Design-Technology Co-Optimization (DTCO): Machine-Learning Assisted Modeling Framework., , , , , , , , and . CoRR, (2019)Evaluation of SRAM Vmin shift induced by random telegraph noise (RTN): physical understanding and prediction method., , , , , and . ISCAS, page 1-4. IEEE, (2018)New insights into the HCI degradation of pass-gate transistor in advanced FinFET technology., , , , , , , , , and 3 other author(s). IRPS, page 3-1. IEEE, (2018)A 3D multi-layer CMOS-RRAM accelerator for neural network., , , , , , and . 3DIC, page 1-5. IEEE, (2016)