( en | de | ru )

 

Disambiguation of "Dutt, Nikil"

Author of the publication

copydeleteadd this publication to your clipboard
Self-awareness in Cyber-Physical Systems: Recent Developments and Open Challenges

, , , , , , and . Design, Automation & Test in Europe Conference & Exhibition (DATE), page 1--6. IEEE, (2023)
DOI: 10.23919/DATE56975.2023.10137197

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Nikil Merani

Som Dutt

Dutt Someshwar

Ulrich Dutt

Horst Dutt

 

Other publications of authors with the same name

Analysis of the Performance of Coarse-Grain Reconfigurable Architectures with Different Processing Element Configurations, , , and . Proceedings of the International Workshop on Application Specific Processors, (2003)Customizing Software Toolkits for Embedded Systems-On-Chip., , and . DIPES, volume 189 of IFIP Conference Proceedings, page 87-98. Kluwer, (2000)ISEGEN: Generation of High-Quality Instruction Set Extensions by Iterative Improvement, , , , and . CoRR, (2007)Generic Pipelined Processor Modeling and High Performance Cycle-Accurate Simulator Generation, and . CoRR, (2007)Data Partitioning Techniques for Partially Protected Caches to Reduce Soft Error Induced Failures., , , and . DIPES, volume 271 of IFIP, page 213-225. Springer, (2008)A Unified code generation approach using mutation scheduling., , and . Code Generation for Embedded Processors, page 203-218. Kluwer, (1994)Novel Brain-Derived Algorithms Scale Linearly with Number of Processing Elements., , , , , , , and . PARCO, volume 15 of Advances in Parallel Computing, page 767-776. IOS Press, (2007)A hypergraph-based model for port allocation on multiple-register-file VLIW architectures., , and . Int. J. Parallel Program., 23 (6): 499-513 (1995)Design Methodology for Responsive and Rrobust MIMO Control of Heterogeneous Multicores., , , , , and . IEEE Trans. Multi Scale Comput. Syst., 4 (4): 944-951 (2018)Optimal Application Mapping and Scheduling for Network-on-Chips with Computation in STT-RAM Based Router., , , and . IEEE Trans. Computers, 68 (8): 1174-1189 (2019)