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Disambiguation of "Tsuchiya, Akira"

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36-Gb/s CDR IC using simple passive loop filter combined with passive load in phase detector.

, , , , , , , and . ISOCC, page 61-62. IEEE, (2016)

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Akira Hayashima

Naotsugu Tsuchiya

Akira Hori

Akira Satake

Akira Hayashima

 

Other publications of authors with the same name

Perturbation-immune radiation-hardened PLL with a switchable DMR structure., , and . IOLTS, page 128-132. IEEE, (2013)Optimization Technique of Memory Traffic for FPGA-Based Image Processing System., , , , and . ISOCC, page 46-47. IEEE, (2019)Statistical Gate Delay Model for Multiple Input Switching., , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 92-A (12): 3070-3078 (2009)Si-Substrate Modeling toward Substrate-Aware Interconnect Resistance and Inductance Extraction in SoC Design., , , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 89-A (12): 3560-3568 (2006)Representative Frequency for Interconnect R(f)L(f)C Extraction., , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 86-A (12): 2942-2951 (2003)Design of a 45 Gb/s, 98 fJ/bit, 0.02 mm2 Transimpedance Amplifier with Peaking-Dedicated Inductor in 65-nm CMOS., , , , , , and . IEICE Trans. Electron., 103-C (10): 489-496 (2020)Implementation of Low-Energy LSTM with Parallel and Pipelined Algorithm in Small-Scale FPGA., , , and . ICEIC, page 1-4. IEEE, (2021)5-Gb/s PAM4 Transmitter IC Using Compensation Circuit in an 180-nm CMOS., , , and . ICEIC, page 1-4. IEEE, (2021)Capacitor Under Pad for Small Area Integration of High-Speed Signal-to-Differential Amplifier., , , , , and . ICEIC, page 1-4. IEEE, (2022)A Fine-Tuning Phase Shifter with Vector Synthesizer Using 65-nm CMOS for Beamforming in 24-GHz Band., , , , and . ICECS 2022, page 1-4. IEEE, (2022)