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A 0.2-to-2.0GHz 65nm CMOS receiver without LNA achieving ≫11dBm IIP3 and ≪6.5 dB NF., , , , and . ISSCC, page 222-223. IEEE, (2009)A 1.5-to-5.0GHz input-matched +2dBm P1dB all-passive switched-capacitor beamforming receiver front-end in 65nm CMOS., , , and . ISSCC, page 174-176. IEEE, (2012)Improving harmonic rejection for spectrum sensing using crosscorrelation., , , , , and . ESSCIRC, page 361-364. IEEE, (2012)A 2.5-10-GHz clock multiplier unit with 0.22-ps RMS jitter in standard 0.18-μm CMOS., , , , and . IEEE J. Solid State Circuits, 39 (11): 1862-1872 (2004)Simplified Harmonic Rejection Mixer Analysis and Design Based on a Filtered Periodic Impulse Model., , and . IEEE Trans. Circuits Syst. II Express Briefs, 68 (7): 2292-2296 (2021)Systematic comparison of HF CMOS transconductors., and . IEEE Trans. Circuits Syst. II Express Briefs, 50 (10): 728-741 (2003)Jitter Analysis and a Benchmarking Figure-of-Merit for Phase-Locked Loops., , , and . IEEE Trans. Circuits Syst. II Express Briefs, 56-II (2): 117-121 (2009)Theoretical Analysis of Highly Linear Tunable Filters Using Switched-Resistor Techniques., , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 55-I (11): 3641-3654 (2008)Simplified Unified Analysis of Switched-RC Passive Mixers, Samplers, and N-Path Filters Using the Adjoint Network., and . IEEE Trans. Circuits Syst. I Regul. Pap., 64-I (10): 2714-2725 (2017)An In-Band Full-Duplex Radio Receiver With a Passive Vector Modulator Downmixer for Self-Interference Cancellation., , and . IEEE J. Solid State Circuits, 50 (12): 3003-3014 (2015)