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Disambiguation of "Shih, Ishiang"

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A Top-Down Design Methodology Encompassing Components Variations Due to Wide-Range Operation in Frequency Synthesizer PLLs.

, , , , and . IEEE Trans. Very Large Scale Integr. Syst., 24 (6): 2050-2061 (2016)

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Yichang Shih

Shih-En Shih

Ho-Sang Shih

Ming-Hsiang Shih

Abdel-Fattah Shihada

 

Other publications of authors with the same name

A simple analog CMOS design tool using transistor dimension-independent parameters., , and . ISCAS, page 1067-1070. IEEE, (2013)Optimization of LC-VCO tuning range under different inductor/varactor losses limitations., , , and . CCECE, page 1-5. IEEE, (2014)Track and hold for Giga-sample ADC applications using CMOS technology., , and . ISCAS, page 2725-2728. IEEE, (2012)A 0.35-V bulk-driven self-biased OTA with rail-to-rail input range in 65 nm CMOS., , , and . ISCAS, page 257-260. IEEE, (2015)A 0.6V-supply bandgap reference in 65 nm CMOS., , , and . NEWCAS, page 1-4. IEEE, (2015)Analytical comparison between passive loop filter topologies for frequency synthesizer PLLs., , and . NEWCAS, page 1-4. IEEE, (2013)A Top-Down Design Methodology Encompassing Components Variations Due to Wide-Range Operation in Frequency Synthesizer PLLs., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 24 (6): 2050-2061 (2016)An Ultra-Low-Voltage CMOS Process-Insensitive Self-Biased OTA With Rail-to-Rail Input Range., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 62-I (10): 2380-2390 (2015)Grouping Fault Detection Protocol under Dynamic Network Environments., , , and . PDPTA, page 151-155. CSREA Press, (2010)A 0.55-V 1-GHz frequency synthesizer PLL for ultra-low-voltage ultra-low-power applications., , , and . LASCAS, page 1-4. IEEE, (2015)