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Multiplierless filter-bank based multicarrier system by using canonical signed digit representation.

, , , and . Wirel. Commun. Mob. Comput., 16 (5): 563-577 (2016)

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A High-Speed Low-Complexity VLSI SISO Architecture., , , , and . APCCAS, page 1512-1515. IEEE, (2006)Efficient utilization of imprecise computational blocks for hardware implementation of imprecision tolerant applications., , and . Microelectron. J., (2017)Lifetime improvement by exploiting aggressive voltage scaling during runtime of error-resilient applications., , , , , and . Integr., (2018)Algorithm and FPGA implementation of interpolation-based soft output mmse mimo detector for 3GPP LTE., , and . IET Commun., 8 (4): 492-499 (2014)Reliability aware throughput management of chip multi-processor architecture via thread migration., , , and . J. Supercomput., 72 (4): 1363-1380 (2016)An analytical method for reliability aware instruction set extension., , and . J. Supercomput., 67 (1): 104-130 (2014)Customized pipeline and instruction set architecture for embedded processing engines., , and . J. Supercomput., 68 (2): 948-977 (2014)Implementation-aware selection of the custom instruction set for extensible processors., , , , , and . Microprocess. Microsystems, 38 (7): 681-691 (2014)Instruction set architectural guidelines for embedded packet-processing engines., , and . J. Syst. Archit., 58 (3-4): 112-125 (2012)Low-power data-driven dynamic logic (D3L) CMOS devices., , and . ISCAS, page 752-755. IEEE, (2000)