Author of the publication

Analysis of Memory Latencies in Multi-Processor Systems.

, , , and . WCET, volume 1 of OASIcs, Internationales Begegnungs- und Forschungszentrum fuer Informatik (IBFI), Schloss Dagstuhl, Germany, (2005)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Failure analysis of a network-on-chip for real-time mixed-critical systems., , , , and . DATE, page 1-4. European Design and Automation Association, (2014)A system-level FPGA design methodology for video applications with weakly-programmable hardware components., , and . J. Real-Time Image Processing, 13 (2): 291-309 (2017)Modelling and designing reliable on-chip-communication devices in MPSoCs with real-time requirements., and . ETFA, page 1465-1472. IEEE, (2008)From Model to Requirements: Pattern-Based Analysis in Distributed Development of Embedded Systems., , and . IESS, volume 184 of IFIP, page 35-44. Springer, (2005)Safety, Efficiency and Autonomy - Mastering Conflicting Trends in Embedded Systems Design.. DIPES/BICC, volume 329 of IFIP Advances in Information and Communication Technology, page 5-6. Springer, (2010)An approach for physical topology exploration in wired bus networks., , and . ISCAS, page 205-208. IEEE, (2015)Selective congestion control for mixed-critical networks-on-chip., , and . Integr., (2019)Adaptive load distribution in mixed-critical Networks-on-Chip., , , and . ASP-DAC, page 732-737. IEEE, (2017)Self-Aware Network-on-Chip Control in Real-Time Systems., , and . IEEE Des. Test, 35 (5): 19-27 (2018)Roundtable: Machine Learning for Embedded Systems: Hype or Lasting Impact?, , , , , , and . IEEE Des. Test, 35 (6): 86-93 (2018)