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A design assembly framework for FPGA back-end acceleration.

, and . Microprocess. Microsystems, 38 (8): 889-898 (2014)

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High-Level Specification of Runtime Reconfigurable Designs., and . ERSA, page 280-283. CSREA Press, (2007)A design assembly framework for FPGA back-end acceleration., and . Microprocess. Microsystems, 38 (8): 889-898 (2014)Processor Reconfiguration Through Instruction-Set Metamorphosis., and . Computer, 26 (3): 11-18 (1993)Image Processing on a Custom Computing Platform., and . FPL, volume 849 of Lecture Notes in Computer Science, page 156-167. Springer, (1994)Engineering of Configurable Systems, II Guest Editor's Foreword., and . J. Supercomput., 26 (3): 219-220 (2003)The (empty?) Promise of FPGA Supercomputing.. Dynamically Reconfigurable Architectures, volume 06141 of Dagstuhl Seminar Proceedings, Internationales Begegnungs- und Forschungszentrum fuer Informatik (IBFI), Schloss Dagstuhl, Germany, (2006)Graph Analytics on Hybrid System (GAHS) Case Study: PageRank., and . IPDPS Workshops, page 160-167. IEEE, (2021)Domain-Specific Modeling and Optimization for Graph Processing on FPGAs., , and . ARC, volume 12700 of Lecture Notes in Computer Science, page 315-326. Springer, (2021)Discovering Reusable Hardware Using Birthmarking Techniques., and . IRI, page 106-113. IEEE Computer Society, (2015)A Run-Time Reconfigurable Engine for Image Interpolation., , and . FCCM, page 88-95. IEEE Computer Society, (1998)