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Checking signal transition graph implementability by symbolic BDD traversal., , , , , and . ED&TC, page 325-332. IEEE Computer Society, (1995)Symbolic Analysis of Bounded Petri Nets., , and . IEEE Trans. Computers, 50 (5): 432-448 (2001)Hierarchical gate-level verification of speed-independent circuits., , and . ASYNC, page 128-137. IEEE Computer Society, (1995)A new look at the conditions for the synthesis of speed-independent circuits., , and . Great Lakes Symposium on VLSI, page 230-. IEEE Computer Society, (1995)Petri Net Analysis Using Boolean Manipulation., , , and . Application and Theory of Petri Nets, volume 815 of Lecture Notes in Computer Science, page 416-435. Springer, (1994)Checking Delay-Insensitivity: 104 Gates and Beyond., , , , and . ASYNC, page 149-157. IEEE Computer Society, (2002)A generalized vision of some parallel bidiagonal systems solvers., , , and . International Conference on Supercomputing, page 404-411. ACM, (1994)Automatic Generation of Synchronous Test Patterns for Asynchronous Circuits., , , and . DAC, page 620-625. ACM Press, (1997)Verification of Asynchronous Circuits by BDD-based Model Checking of Petri Nets., , and . Application and Theory of Petri Nets, volume 935 of Lecture Notes in Computer Science, page 374-391. Springer, (1995)Review of General and Toeplitz Vector Bidiagonal Solvers., , , and . Parallel Comput., 22 (8): 1091-1126 (1996)