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Disambiguation of "Valverde, Juan"

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A dynamically adaptable bus architecture for trading-off among performance, consumption and dependability in Cyber-Physical Systems.

, , , , , , and . FPL, page 1-4. IEEE, (2014)

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Juan Fernández Valverde

Isabel Valverde

Hsiao-Mei Juan

Alexander Juan

Elias Valverde

 

Other publications of authors with the same name

A Fast Prototyping Workflow for Reconfigurable SDR Applications., , , and . ReCoSoC, page 66-73. IEEE, (2019)Using SRAM Based FPGAs for Power-Aware High Performance Wireless Sensor Networks., , , , , and . Sensors, 12 (3): 2667-2692 (2012)Execution modeling in self-aware FPGA-based architectures for efficient resource management., , , , , and . ReCoSoC, page 1-8. IEEE, (2015)Power-aware multi-objective evolvable hardware system on an FPGA., , , and . AHS, page 61-68. IEEE, (2014)Power management techniques in an FPGA-based WSN node for high performance applications., , , , , and . ReCoSoC, page 1-8. IEEE, (2012)Design of OpenCL-Compatible Multithreaded Hardware Accelerators with Dynamic Support for Embedded FPGAs, , and . (2015)Design of OpenCL-compatible multithreaded hardware accelerators with dynamic support for embedded FPGAs., , and . ReConFig, page 1-7. IEEE, (2015)FPGA-Based High-Performance Embedded Systems for Adaptive Edge Computing in Cyber-Physical Systems: The ARTICo3 Framework., , , , , and . Sensors, 18 (6): 1877 (2018)A dynamically adaptable bus architecture for trading-off among performance, consumption and dependability in Cyber-Physical Systems., , , , , , and . FPL, page 1-4. IEEE, (2014)Dynamic management of multikernel multithread accelerators using Dynamic Partial Reconfiguration., , , and . ReCoSoC, page 1-7. IEEE, (2014)