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The negative bias temperature instability in MOS devices: A review., and . Microelectron. Reliab., 46 (2-4): 270-286 (2006)Dependence of Post-Breakdown Conduction on Gate Oxide Thickness., , and . Microelectron. Reliab., 42 (9-11): 1481-1484 (2002)Impacts of NBTI and PBTI on SRAM static/dynamic noise margins and cell failure probability., , , , , and . Microelectron. Reliab., 49 (6): 642-649 (2009)Influence and model of gate oxide breakdown on CMOS inverters., , , , and . Microelectron. Reliab., 43 (9-11): 1439-1444 (2003)The resilience wall: Cross-layer solution strategies., , , , , , , , , and 3 other author(s). VLSI-DAT, page 1-11. IEEE, (2014)Analyzing path delays for accelerated testing of logic chips., , , , , , , and . IRPS, page 6. IEEE, (2015)A critical analysis of sampling-based reconstruction methodology for dielectric breakdown systems (BEOL/MOL/FEOL)., , , , , and . IRPS, page 2. IEEE, (2015)Circuit implications of gate oxide breakdown., , and . Microelectron. Reliab., 43 (8): 1193-1197 (2003)Controversial issues in negative bias temperature instability., , and . Microelectron. Reliab., (2018)Influence of the SiO2 layer thickness on the degradation of HfO2/SiO2 stacks subjected to static and dynamic stress conditions., , , , and . Microelectron. Reliab., 47 (4-5): 544-547 (2007)