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Fault table generation using Graphics Processing Units., and . HLDVT, page 60-67. IEEE Computer Society, (2009)Efficient don't care computation for hierarchical designs., , and . ISCAS, IEEE, (2006)A design flow to optimize circuit delay by using standard cells and PLAs., , , , , and . ACM Great Lakes Symposium on VLSI, page 217-222. ACM, (2006)Robust window-based multi-node technology-independent logic minimization., , and . ACM Great Lakes Symposium on VLSI, page 357-362. ACM, (2009)Boolean satisfiability on a graphics processor., and . ACM Great Lakes Symposium on VLSI, page 123-126. ACM, (2010)Sorting Binary Numbers in Hardware - A Novel Algorithm and its Implementation., , and . ISCAS, page 2225-2228. IEEE, (2009)Highly parallel decoding of space-time codes on graphics processing units., , , , and . Allerton, page 1262-1269. IEEE, (2009)On-chip bidirectional wiring for heavily pipelined systems using network coding., , , and . ICCD, page 131-136. IEEE Computer Society, (2009)A probabilistic method to determine the minimum leakage vector for combinational designs., , and . ISCAS, IEEE, (2006)Towards acceleration of fault simulation using graphics processing units., and . DAC, page 822-827. ACM, (2008)