Author of the publication

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Test point insertion for RSFQ circuits., and . ISCAS, page 1-4. IEEE, (2017)On-Chip Power Noise Reduction Techniques in High Performance SoC-Based Integrated Circuits., , , and . SoCC, page 309-312. IEEE, (2005)Behavioral Verilog-A Model of Superconductor-Ferromagnetic Transistor., and . ISCAS, page 1-5. IEEE, (2018)PMTJ Temperature Sensor Utilizing VCMA., and . ISCAS, page 1-5. IEEE, (2019)Multi-aggressor capacitive and inductive coupling noise modeling and mitigation., , and . Microelectron. J., 43 (4): 235-243 (2012)Monolithic voltage conversion in low-voltage CMOS technologies., , , and . Microelectron. J., 36 (9): 863-867 (2005)Exploiting the on-chip inductance in high-speed clock distribution networks., , and . IEEE Trans. Very Large Scale Integr. Syst., 9 (6): 963-973 (2001)Analysis of buck converters for on-chip integration with a dual supply voltage microprocessor., , , and . IEEE Trans. Very Large Scale Integr. Syst., 11 (3): 514-522 (2003)Channel width tapering of serially connected MOSFET's with emphasis on power dissipation., and . IEEE Trans. Very Large Scale Integr. Syst., 2 (1): 100-114 (1994)Corrections to Ünified Logical Effort - A Method for Delay Evaluation and Minimization in Logic Paths With RC Interconnect" May 10 689-696., , , and . IEEE Trans. Very Large Scale Integr. Syst., 18 (8): 1262 (2010)