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Combining static and dynamic array detection for binary synthesis with multiple memory ports., and . Des. Autom. Embed. Syst., 15 (1): 1-18 (2011)The effect of unrolling and inlining for Python bytecode optimizations., and . SYSTOR, page 14. ACM, (2009)Hybrid type legalization for a sparse SIMD instruction set., and . ACM Trans. Archit. Code Optim., 10 (3): 11:1-11:14 (2013)Profile Guided Optimization without Profiles: A Machine Learning Approach., and . CoRR, (2021)Reducing Memory Constraints in Modulo Scheduling Synthesis for FPGAs., , and . ACM Trans. Reconfigurable Technol. Syst., 3 (3): 15:1-15:19 (2010)Automatic memory partitioning: increasing memory parallelism via data structure partitioning., and . CODES+ISSS, page 155-162. ACM, (2010)Optimizing wait-states in the synthesis of memory references with unpredictable latencies., , and . ICSAMOS, page 270-277. IEEE, (2011)Glow: Graph Lowering Compiler Techniques for Neural Networks., , , , , , , , , and 3 other author(s). CoRR, (2018)Finding the best compromise in compiling compound loops to Verilog., , and . J. Syst. Archit., 56 (9): 474-486 (2010)Using memory profile analysis for automatic synthesis of pointers code., and . ACM Trans. Embed. Comput. Syst., 12 (3): 68:1-68:21 (2013)