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Synchronous Up/Down Binary Counter for LUT FPGAs with Counting Frequency Independent of Counter Size.

, and . FPGA, page 159-165. ACM, (1997)

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High-Radix Design of a Scalable Modular Multiplier., , and . CHES, volume 2162 of Lecture Notes in Computer Science, page 185-201. Springer, (2001)Scalable and Unified Hardware to Compute Montgomery Inverse in GF(p) and GF(2)., , , and . CHES, volume 2523 of Lecture Notes in Computer Science, page 484-499. Springer, (2002)Multi-operand Floating-Point Addition.. IEEE Symposium on Computer Arithmetic, page 161-168. IEEE Computer Society, (2009)A design methodology for networks of online modules and its application to the Levinson-Durbin algorithm., and . IEEE Trans. Very Large Scale Integr. Syst., 12 (1): 52-66 (2004)A Scalable and Unified Multiplier Architecture for Finite Fields GF(p) and GF(2m)., , and . CHES, volume 1965 of Lecture Notes in Computer Science, page 277-292. Springer, (2000)An Algorithm and Hardware Architecture for Integrated Modular Division and Multiplication in GF(p) and GF(2n)., and . ASAP, page 247-257. IEEE Computer Society, (2004)On the Design of High-Radix On-Line Division for Long Precision., and . IEEE Symposium on Computer Arithmetic, page 44-51. IEEE Computer Society, (1999)Carry-Save Representation Is Shift-Unsafe: The Problem and Its Solution., , and . IEEE Trans. Computers, 55 (5): 630-635 (2006)Efficient scalable VLSI architecture for Montgomery inversion in GF( p)., and . Integr., 37 (2): 103-120 (2004)A parallel k-partition method to perform Montgomery Multiplication., , and . ASAP, page 251-254. IEEE Computer Society, (2011)