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A Multi-ported Memory Compiler Utilizing True Dual-Port BRAMs.

, and . FCCM, page 140-147. IEEE Computer Society, (2016)

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39 000-Subexposures/s Dual-ADC CMOS Image Sensor With Dual-Tap Coded-Exposure Pixels for Single-Shot HDR and 3-D Computational Imaging., , , , , , , , , and 8 other author(s). IEEE J. Solid State Circuits, 58 (11): 3150-3163 (November 2023)Enabling Mixed-Timing NoCs for FPGAs: Reconfigurable Synthesizable Synchronization FIFOs., and . FPL, page 312-318. IEEE, (2021)Modular SRAM-Based Binary Content-Addressable Memories., and . FCCM, page 207-214. IEEE Computer Society, (2015)Modular Switched Multiported SRAM-Based Memories., and . ACM Trans. Reconfigurable Technol. Syst., 9 (3): 22:1-22:26 (2016)Revisiting Deep Learning Parallelism: Fine-Grained Inference Engine Utilizing Online Arithmetic., and . FPT, page 383-386. IEEE, (2019)Noema: Hardware-Efficient Template Matching for Neural Population Pattern Detection., , , , and . MICRO, page 522-534. ACM, (2021)Synthesizable Synchronization FIFOs Utilizing the Asynchronous Pulse-Based Handshake Protocol.. NorCAS, page 1-7. IEEE, (2020)Accelerated Approximate Nearest Neighbors Search Through Hierarchical Product Quantization., , and . FPT, page 90-98. IEEE, (2019)Interleaved Architectures for High-Throughput Synthesizable Synchronization FIFOs., and . ASYNC, page 41-48. IEEE Computer Society, (2017)Modular Block-RAM-Based Longest-Prefix Match Ternary Content-Addressable Memories., , and . FPL, page 243-250. IEEE Computer Society, (2018)