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On error-correction performance and implementation of polar code list decoders for 5G.

, , , and . Allerton, page 443-449. IEEE, (2017)

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Improved Bit-Flipping Algorithm for Successive Cancellation Decoding of Polar Codes., , and . IEEE Trans. Commun., 67 (1): 61-72 (2019)Reduced-memory high-throughput fast-SSC polar code decoder architecture., , and . SiPS, page 1-6. IEEE, (2017)Power-delay analysis of an ABACUS parallel integer multiplier VLSI implementation., and . ICEAC, page 1-4. IEEE, (2015)An integrated approach to system-level CPU and memory energy efficiency on computing systems., , and . ICEAC, page 1-6. IEEE, (2012)High-Throughput VLSI Architecture for Soft-Decision Decoding with ORBGRAND., , , , and . ICASSP, page 8288-8292. IEEE, (2021)Demo: Universal Soft-Detection Decoder with Ultra-Low Energy Consumption Using ORBGRAND., , , , , , , , and . WoWMoM, page 337-339. IEEE, (2023)Modeling and Simulation for the Operative Service Delivery Planning in the Context of Product-Service Systems., , , and . WSC, page 1936-1947. IEEE, (2023)High-Throughput and Energy-Efficient VLSI Architecture for Ordered Reliability Bits GRAND., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 30 (6): 681-693 (2022)Neural Successive Cancellation Flip Decoding of Polar Codes., , , , and . J. Signal Process. Syst., 93 (6): 631-642 (2021)High-Throughput VLSI Architecture for GRAND., , , and . SiPS, page 1-6. IEEE, (2020)