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Disambiguation of "Onodera, Hidetoshi"

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Layout Generator with Flexible Grid Assignment for Area Efficient Standard Cell.

, , and . IPSJ Trans. Syst. LSI Des. Methodol., (2015)

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Kaoru Onodera

Keiichi Onodera

Hidetoshi Yamabe

 

Other publications of authors with the same name

Power-bandwidth trade-off analysis of multi-stage inverter-type transimpedance amplifier for optical communication., , and . MWSCAS, page 795-798. IEEE, (2017)Analysis and comparison of XOR cell structures for low voltage circuit design., , and . ISQED, page 703-708. IEEE, (2013)Variation-aware Flip-Flop energy optimization for ultra low voltage operation., , , and . SoCC, page 17-22. IEEE, (2014)On-chip temperature and process variation sensing using a reconfigurable Ring Oscillator., , and . VLSI-DAT, page 1-4. IEEE, (2017)Worst-case delay analysis considering the variability of transistors and interconnects., , and . ISPD, page 35-42. ACM, (2007)An area effective forward/reverse body bias generator for within-die variability compensation., , and . A-SSCC, page 217-220. IEEE, (2011)Performance optimization by track swapping on critical paths utilizing random variations for FPGAS., , , and . FPL, page 503-506. IEEE, (2008)A Yield and Speed Enhancement Technique Using Reconfigurable Devices Against Within-Die Variations on the Nanometer Regime., , , , , , and . FPL, page 1-4. IEEE, (2006)Multi-Level Optimization for Large Fan-In Optical Logic Circuits Using Integrated Nanophotonics., , , , , , , and . ICRC, page 1-8. IEEE, (2018)An Integrated Optical Parallel Multiplier Exploiting Approximate Binary Logarithms Towards Light Speed Data Processing., , , , and . ICRC, page 1-6. IEEE, (2018)