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Disambiguation of "Onodera, Hidetoshi"

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Layout Generator with Flexible Grid Assignment for Area Efficient Standard Cell.

, , and . IPSJ Trans. Syst. LSI Des. Methodol., (2015)

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Kaoru Onodera

Keiichi Onodera

Hidetoshi Yamabe

 

Other publications of authors with the same name

Variation-aware Flip-Flop energy optimization for ultra low voltage operation., , , and . SoCC, page 17-22. IEEE, (2014)An area effective forward/reverse body bias generator for within-die variability compensation., , and . A-SSCC, page 217-220. IEEE, (2011)Worst-case delay analysis considering the variability of transistors and interconnects., , and . ISPD, page 35-42. ACM, (2007)On-chip temperature and process variation sensing using a reconfigurable Ring Oscillator., , and . VLSI-DAT, page 1-4. IEEE, (2017)Power-bandwidth trade-off analysis of multi-stage inverter-type transimpedance amplifier for optical communication., , and . MWSCAS, page 795-798. IEEE, (2017)Standard cell libraries with various driving strength cells for 0.13, 0.18 and 0.35 μm technologies., , and . ASP-DAC, page 589-590. ACM, (2003)A performance optimization method by gate sizing using statistical static timing analysis., and . ISPD, page 111-116. ACM, (2000)An Optical Accelerator for Deep Neural Network Based on Integrated Nanophotonics., , , , and . ICRC, page 95-101. IEEE, (2020)Dependable VLSI: device, design and architecture: how should they cooperate?, , , and . ASP-DAC, page 859-860. IEEE, (2009)Interconnect RL extraction at a single representative frequency., , and . ASP-DAC, page 515-520. IEEE, (2006)