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Optimizing test architecture of 3D stacked ICs for partial stack/complete stack using hard SoCs.

S. Roy, C. Giri, and H. Rahaman. IDT, page 1-3. IEEE, (2013)

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Hasibur Rahaman

Md Hafizur Rahman

Mohammad Saidur Rahaman

Other publications of authors with the same name

BIST Design for Detecting Multiple Stuck-Open Faults in CMOS Circuits Using Transition Count.H. Rahaman, D. Das, and B. Bhattacharya. J. Comput. Sci. Technol., 17 (6): 731-737 (2002)Derivation of Reduced Test Vectors for Bit-Parallel Multipliers over GF(2^m).H. Rahaman, J. Mathew, D. Pradhan, and A. Jabir. IEEE Trans. Computers, 57 (9): 1289-1294 (2008)Design of Content Addressable Memory Architecture Using Carbon Nanotube Field Effect Transistors.D. Das, A. Roy, and H. Rahaman. VDAT, volume 7373 of Lecture Notes in Computer Science, page 233-242. Springer, (2012)A testing scheme for mixed-control based reversible circuits.B. Mondal, C. Bandyopadhyay, and H. Rahaman. ISED, page 96-100. IEEE, (2016)Diagnosis of SMGF in ESOP Based Reversible Logic Circuit.B. Mondal, C. Bandyopadhyay, D. Kole, J. Mathew, and H. Rahaman. ISED, page 89-93. IEEE Computer Society, (2014)Hausdorff Distance Driven L-Shape Matching Based Layout Decomposition for E-Beam Lithography.A. Sinharay, P. Roy, and H. Rahaman. VDAT, volume 711 of Communications in Computer and Information Science, page 287-295. Springer, (2017)All optical implementation of Mach-Zehnder interferometer based reversible sequential circuit.P. Dutta, C. Bandyopadhyay, and H. Rahaman. VDAT, page 1-2. IEEE, (2014)Synthesis aware sample preparation techniques using random sample sets in DMFB.P. Roy, S. Chakraborty, and H. Rahaman. VDAT, page 1-6. IEEE, (2016)3D integration in biochips: New proposed architectures for 3D applications in ATDA based digital microfluidic biochips.P. Roy, P. Howladar, R. Dastidar, H. Rahaman, and P. Dasgupta. DTIS, page 1-6. IEEE, (2015)A heuristic method for obstacle avoiding group Steiner tree construction.T. Samanta, R. Sardar, H. Rahaman, P. Dasgupta, and B. Bhattacharya. SLIP, page 21. ACM, (2012)

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Disambiguation of "Rahaman, Hafizur"

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Optimizing test architecture of 3D stacked ICs for partial stack/complete stack using hard SoCs.

Please choose a person to relate this publication to

Hasibur Rahaman

Md Hafizur Rahman

Mohammad Saidur Rahaman

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Rahaman, Hafizur"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Optimizing test architecture of 3D stacked ICs for partial stack/complete stack using hard SoCs.

Please choose a person to relate this publication to

Hasibur Rahaman

Md Hafizur Rahman

Mohammad Saidur Rahaman

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
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URL
DOI
BibTeX
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APA
Chicago
DIN 1505
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Optimizing test architecture of 3D stacked ICs for partial stack/complete stack using hard SoCs.