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Sequential and Parallel Code Sections are Different: they may require different Processors.

, and . PARMA-DITAM@HiPEAC, page 13-18. ACM, (2015)

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Towards a large number of pipeline processors in a tightly coupled multiprocessor using no cache., and . ICS, page 611-620. ACM, (1988)The L-TAGE Branch Predictor.. J. Instruction-Level Parallelism, (2007)Sequential and Parallel Code Sections are Different: they may require different Processors., and . PARMA-DITAM@HiPEAC, page 13-18. ACM, (2015)Controlling and sequencing a heavily pipelined floating-point operator., and . MICRO, page 111-114. ACM / IEEE Computer Society, (1992)MIDEE: smoothing branch and instruction cache miss penalties on deep pipelines., and . MICRO, page 193-201. ACM / IEEE Computer Society, (1993)BADCO: Behavioral Application-Dependent Superscalar Core model., , and . ICSAMOS, page 58-67. IEEE, (2012)Out-of-Order Execution may not be Cost-Effective on Processors Featuring Simultaneous Multithreading., and . HPCA, page 64-67. IEEE Computer Society, (1999)A Case for Partial Co-allocation Constraints in Compressed Caches., and . SAMOS, volume 13227 of Lecture Notes in Computer Science, page 65-77. Springer, (2021)Speculative software management of datapath-width for energy optimization., , , and . LCTES, page 78-87. ACM, (2004)Tarantula: A Vector Extension to the Alpha Architecture., , , , , , , , , and 1 other author(s). ISCA, page 281-292. IEEE Computer Society, (2002)