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A logic-compatible embedded flash memory featuring a multi-story high voltage switch and a selective refresh scheme., , и . VLSIC, стр. 130-131. IEEE, (2012)Fault-tolerant ripple-carry binary adder using partial triple modular redundancy (PTMR)., , и . ISCAS, стр. 41-44. IEEE, (2015)A multi-story power delivery technique for 3D integrated circuits., , , и . ISLPED, стр. 57-62. ACM, (2008)A 2.1 pJ/bit, 8 Gb/s Ultra-Low Power In-Package Serial Link Featuring a Time-based Front-end and a Digital Equalizer., , , и . A-SSCC, стр. 187-190. IEEE, (2018)A Probabilistic Compute Fabric Based on Coupled Ring Oscillators for Solving Combinatorial Optimization Problems., , , и . IEEE J. Solid State Circuits, 56 (9): 2870-2880 (2021)Circuit Design and Modeling Techniques for Enhancing the Clock-Data Compensation Effect Under Resonant Supply Noise., , и . IEEE J. Solid State Circuits, 45 (10): 2130-2141 (2010)A Time-Based Intra-Memory Computing Graph Processor Featuring A* Wavefront Expansion and 2-D Gradient Control., , и . IEEE J. Solid State Circuits, 56 (7): 2281-2290 (2021)Leakage Power Analysis and Reduction for Nanoscale Circuits., , , , и . IEEE Micro, 26 (2): 68-80 (2006)A 0.4-1.6GHz spur-free bang-bang digital PLL in 65nm with a D-flip-flop based frequency subtractor circuit., , и . VLSIC, стр. 140-. IEEE, (2015)A multi-phase VCO quantizer based adaptive digital LDO in 65nm CMOS technology., и . ISCAS, стр. 1-4. IEEE, (2017)