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Optimum vectorization of scalable synchronous dataflow graphs., , , and . ASAP, page 285-296. IEEE, (1993)Advanced digital receiver principles and technologies for PCS., and . IEEE Commun. Mag., 33 (1): 68-78 (1995)A 40 Mb/s soft-output Viterbi decoder., and . IEEE J. Solid State Circuits, 30 (7): 812-818 (July 1995)The programmable platform: does one size fit all?, , and . DATE, page 226-227. IEEE Computer Society, (2001)A Generic Design Flow for Application Specific Processor Customization through Instruction-Set Extensions (ISEs)., , , and . SAMOS, volume 5657 of Lecture Notes in Computer Science, page 204-214. Springer, (2009)An Aliasing-Free Receiver with Variable Sample Rate Digital Feedback M/T NDA Timing Synchronization., , and . Wireless Personal Communications, 8 (2): 165-183 (1998)An information theoretic analysis of sequential decision-making., , , , and . ISIT, page 3050-3054. IEEE, (2017)Methodical Low-Power ASIP Design Space Exploration., , and . VLSI Signal Processing, 33 (3): 229-246 (2003)Architecture exploration for embedded processors with LISA., , and . Kluwer, (2002)Oversampling Increases the Pre-Log of Noncoherent Fading Channels., , , , and . CoRR, (2014)