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Disambiguation of "Jeon, Young-Deuk"

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A Dual-Channel Pipelined ADC With Sub-ADC Based on Flash-SAR Architecture.

, , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 59-II (11): 741-745 (2012)

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Deuk ju Jeon

Seonghye Jeon

Jinseong Jeon

Heinrich Hans Deuker

Waltraud Deuker

 

Other publications of authors with the same name

A 9.15mW 0.22mm2 10b 204MS/s pipelined SAR ADC in 65nm CMOS., , , , , , and . CICC, page 1-4. IEEE, (2010)A 10b 205MS/s 1mm2 90nm CMOS Pipeline ADC for Flat-Panel Display Applications., , , , , , and . ISSCC, page 458-615. IEEE, (2007)A Dual-Channel Pipelined ADC With Sub-ADC Based on Flash-SAR Architecture., , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 59-II (11): 741-745 (2012)Chiplet Heterogeneous-Integration AI Processor., , , , , , , , , and 5 other author(s). ICEIC, page 1-2. IEEE, (2023)Acquisition-time minimization and merged-capacitor switching techniques for sampling-rate and resolution improvement of CMOS ADCs., , , and . ISCAS, page 451-454. IEEE, (2000)A 12b 50 MHz 3.3V CMOS acquisition time minimized A/D converter., , , , and . ASP-DAC, page 613-616. ACM, (2000)A 12-bit 100-MS/s pipelined ADC in 45-nm CMOS., , , , and . ISOCC, page 405-407. IEEE, (2011)A 2.85mW 0.12mm2 1.0V 11-bit 20-MS/s algorithmic ADC in 65nm CMOS., , , , and . ESSCIRC, page 468-471. IEEE, (2009)A 4.7mW 0.32mm2 10b 30MS/s Pipelined ADC Without a Front-End S/H in 90nm CMOS., , , , and . ISSCC, page 456-615. IEEE, (2007)A 10-bit 30-MS/s successive approximation register analog-to-digital converter for low-power sub-sampling applications., , , and . Microelectron. J., 42 (12): 1335-1342 (2011)