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Mathematical Modeling of Intellectual Property Protection Using Partially-Mergeable Cores., , , и . PDPTA, CSREA Press, (2000)Multi-site test optimization for multi-Vdd SoCs using space- and time- division multiplexing., , , , и . DATE, стр. 1-6. European Design and Automation Association, (2014)Wrapper/TAM co-optimization, constraint-driven test scheduling, and tester data volume reduction for SOCs., , и . DAC, стр. 685-690. ACM, (2002)Test Bus Sizing for System-on-a-Chip., и . IEEE Trans. Computers, 51 (5): 449-459 (2002)Synterface: Efficient Chip-to-World Interfacing for Flow-Based Microfluidic Biochips Using Pin-Count Minimization., , и . ACM Trans. Embed. Comput. Syst., 18 (5s): 54:1-54:21 (2019)Control-Logic Synthesis of Fully Programmable Valve Array Using Reinforcement Learning., , , , , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 43 (1): 277-290 (января 2024)Formal Synthesis of Adaptive Droplet Routing for MEDA Biochips., , , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 41 (8): 2504-2517 (2022)Cross-Contamination Avoidance for Droplet Routing in Digital Microfluidic Biochips., и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 31 (6): 817-830 (2012)Energy-conscious, deterministic I/O device scheduling in hard real-time systems., и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 22 (7): 847-858 (2003)Test Wrapper Design and Optimization Under Power Constraints for Embedded Cores With Multiple Clock Domains., , и . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 26 (8): 1539-1547 (2007)