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Dynamic thermal clock skew compensation using tunable delay buffers.

A. Chakraborty, K. Duraisami, A. Sathanur, P. Sithambaram, L. Benini, A. Macii, E. Macii, and M. Poncino. ISLPED, page 162-167. ACM, (2006)

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Row-Based Power-Gating: A Novel Sleep Transistor Insertion Methodology for Leakage Power Optimization in Nanometer CMOS Circuits.A. Sathanur, L. Benini, A. Macii, E. Macii, and M. Poncino. IEEE Trans. Very Large Scale Integr. Syst., 19 (3): 469-482 (2011)Activity profile driven simultaneous vt assignment and power switch sizing for leakage power minimization in nanometer CMOS designs.A. Sathanur, J. Huisken, J. Stuyt, and H. de Groot. ICECS, page 519-522. IEEE, (2010)On quantifying the figures of merit of power-gating for leakage power minimization in nanometer CMOS circuits.A. Sathanur, A. Calimera, A. Pullini, L. Benini, A. Macii, E. Macii, and M. Poncino. ISCAS, page 2761-2764. IEEE, (2008)Row-based FBB: A design-time optimization for post-silicon tunable circuits.M. Kakoee, A. Sathanur, A. Pullini, and L. Benini. Microelectron. J., 43 (7): 456-465 (2012)Implementation of a thermal management unit for canceling temperature-dependent clock skew variations.A. Chakraborty, K. Duraisami, A. Sathanur, P. Sithambaram, A. Macii, E. Macii, and M. Poncino. Integr., 41 (1): 2-8 (2008)Dynamic Management of Thermally-Induced Clock Skew: An Implementation Perspective.A. Chakraborty, K. Duraisami, A. Sathanur, P. Sithambaram, A. Macii, E. Macii, and M. Poncino. PATMOS, volume 4148 of Lecture Notes in Computer Science, page 214-224. Springer, (2006)Timing-driven row-based power gating.A. Sathanur, A. Pullini, L. Benini, A. Macii, E. Macii, and M. Poncino. ISLPED, page 104-109. ACM, (2007)Interactive presentation: Efficient computation of discharge current upper bounds for clustered sleep transistor sizing.A. Sathanur, A. Calimera, L. Benini, A. Macii, E. Macii, and M. Poncino. DATE, page 1544-1549. EDA Consortium, San Jose, CA, USA, (2007)Fast Computation of Discharge Current Upper Bounds for Clustered Power Gating.A. Sathanur, L. Benini, A. Macii, E. Macii, and M. Poncino. IEEE Trans. Very Large Scale Integr. Syst., 19 (1): 146-151 (2011)Dynamic Thermal Clock Skew Compensation Using Tunable Delay Buffers.A. Chakraborty, K. Duraisami, A. Sathanur, P. Sithambaram, L. Benini, A. Macii, E. Macii, and M. Poncino. IEEE Trans. Very Large Scale Integr. Syst., 16 (6): 639-649 (2008)

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Dynamic thermal clock skew compensation using tunable delay buffers.

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Disambiguation of "Sathanur, Ashoka Visweswara"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Dynamic thermal clock skew compensation using tunable delay buffers.

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Dynamic thermal clock skew compensation using tunable delay buffers.