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A TCP offload accelerator for 10 Gb/s Ethernet in 90-nm CMOS., , , , , , , , , and 5 other author(s). IEEE J. Solid State Circuits, 38 (11): 1866-1875 (2003)Measurements and analysis of SER-tolerant latch in a 90-nm dual-VT CMOS process., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 39 (9): 1536-1543 (2004)A 233-MHz 80%-87% efficient four-phase DC-DC converter utilizing air-core inductors on package., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 40 (4): 838-845 (2005)5-GHz 32-bit integer execution core in 130-nm dual-VT CMOS., , , , , , , , , and 12 other author(s). IEEE J. Solid State Circuits, 37 (11): 1421-1432 (2002)The Astronautics ZS-1 processor., , , , , , , and . ICCD, page 307-310. IEEE, (1988)The ZS-1 Central Processor., , , , , , , and . ASPLOS, page 199-204. ACM Press, (1987)SIGARCH Computer Architecture News 15(5), SIGOPS Operating System Review 21(4), SIGPLAN Notices 22(10).