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A $+$31.5 dBm CMOS RF Doherty Power Amplifier for Wireless Communications.

, , and . IEEE J. Solid State Circuits, 41 (12): 2852-2859 (2006)

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A 50 MHz eight-tap adaptive equalizer for partial-response channels., , , and . IEEE J. Solid State Circuits, 30 (3): 228-234 (March 1995)A $+$31.5 dBm CMOS RF Doherty Power Amplifier for Wireless Communications., , and . IEEE J. Solid State Circuits, 41 (12): 2852-2859 (2006)A power optimized 13-b 5 Msamples/s pipelined analog-to-digital converter in 1.2 μm CMOS., and . IEEE J. Solid State Circuits, 31 (3): 294-303 (1996)A 100 MHz A/D interface for PRML magnetic disk read channels., and . IEEE J. Solid State Circuits, 29 (12): 1606-1613 (December 1994)A 1.9-GHz, 1-W CMOS class-E power amplifier for wireless communications., and . IEEE J. Solid State Circuits, 34 (7): 962-970 (1999)Recent developments in high integration multi-standard CMOS transceivers for personal communication systems., , , , , , , , , and 4 other author(s). ISLPED, page 149-154. ACM, (1998)A 13-bit, 1.4-MS/s sigma-delta modulator for RF baseband channel applications., , and . IEEE J. Solid State Circuits, 33 (10): 1462-1469 (1998)A 10 b, 20 Msample/s, 35 mW pipeline A/D converter., and . IEEE J. Solid State Circuits, 30 (3): 166-172 (March 1995)PLL/DLL System Noise Analysis for Low Jitter Clock Synthesizer Design., , and . ISCAS, page 31-34. IEEE, (1994)A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter., and . IEEE J. Solid State Circuits, 34 (5): 599-606 (1999)