Author of the publication

Correlated Rare Failure Analysis via Asymptotic Probability Evaluation.

, , , , , and . DAC, page 54:1-54:6. ACM, (2017)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

FMSSQP: An efficient global optimization tool for the robust design of Rail-to-Rail Op-Amp., , , and . ASICON, page 1-4. IEEE, (2013)A Folding Strategy for SAT solvers based on Shannon's expansion theorem., , , and . SoCC, page 177-181. IEEE, (2010)An automatic clock tree design system for high-speed VLSI designs: planar clock routing with the treatment of obstacles., and . ISCAS (6), page 258-261. IEEE, (1999)RLCSYN: RLC Equivalent Circuit Synthesis for Structure-Preserved Reduced-order Model of Interconnect., , , and . ISCAS, page 2710-2713. IEEE, (2007)Propagation Delay in RLC Interconnection Networks., and . ISCAS, page 2125-2128. IEEE, (1993)Frequency driven repeater insertion for deep submicron., , , and . ISCAS (5), page 181-184. IEEE, (2004)Optimization of VLSI Allocation., and . ISCAS, page 1065-1068. IEEE, (1995)Efficient SVM-based hotspot detection using spectral clustering., , , and . ISCAS, page 1-4. IEEE, (2017)Correlated Rare Failure Analysis via Asymptotic Probability Evaluation., , , , , and . DAC, page 54:1-54:6. ACM, (2017)Efficient Spatial Variation Modeling of Nanoscale Integrated Circuits Via Hidden Markov Tree., , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 35 (6): 971-984 (2016)