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Disambiguation of "Lee, Hsu-Chieh"

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Symmetrical buffered clock-tree synthesis with supply-voltage alignment.

, , , , and . ASP-DAC, page 447-452. IEEE, (2013)

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Chieh Hsu

Szu-Chieh Hsu

Sheng-chieh Lee

Cheng-Chieh Lee

Hsu-Yi Lee

 

Other publications of authors with the same name

A chip-package-board co-design methodology., and . DAC, page 1082-1087. ACM, (2012)Escape Routing for Staggered-Pin-Array PCBs., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 32 (9): 1347-1356 (2013)Obstacle-Avoiding Free-Assignment Routing for Flip-Chip Designs., , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 33 (2): 224-236 (2014)High variation-tolerant obstacle-avoiding clock mesh synthesis with symmetrical driving trees., , , and . ICCAD, page 452-457. IEEE, (2010)Obstacle-avoiding free-assignment routing for flip-chip designs., , , , , , and . DAC, page 1088-1093. ACM, (2012)Escape routing for staggered-pin-array PCBs., , and . ICCAD, page 306-309. IEEE Computer Society, (2011)Recent research development in flip-chip routing., , and . ICCAD, page 404-410. IEEE, (2010)Symmetrical buffered clock-tree synthesis with supply-voltage alignment., , , , and . ASP-DAC, page 447-452. IEEE, (2013)