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Disambiguation of "Pal, Ajit"

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Loop unrolling with fine grained power gating for runtime leakage power reduction.

, and . VDAT, page 1-6. IEEE, (2014)

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Suraj Ajit

Jisesh Ajitha Sethunadh

Ajit Karmaker

Ajit Lokhande

Ajit Rai

 

Other publications of authors with the same name

Operator Scheduling Revisited: A Multi-objective Perspective for Fine-Grained DVS Architecture., , , and . ACITY (3), volume 178 of Advances in Intelligent Systems and Computing, page 633-648. Springer, (2012)POWER-TRUCTOR: An Integrated Tool Flow for Formal Verification and Coverage of Architectural Power Intent., , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 32 (11): 1801-1813 (2013)Computing area and wire length efficient routes for channels., , , and . VLSI Design, page 196-201. IEEE Computer Society, (1995)Optimal Dual -VT Assignment for Low-Voltage Energy-Constrained CMOS Circuits., and . ASP-DAC/VLSI Design, page 193-198. IEEE Computer Society, (2002)DDSCHED: A distributed dynamic real-time scheduling algorithm., , , and . Scalable Comput. Pract. Exp., (1998)A power-aware wireless sensor network based bridge monitoring system., , and . ICON, page 1-7. IEEE, (2008)An Algorithm for Optimal Logic Design Using Multiplexers.. IEEE Trans. Computers, 35 (8): 755-757 (1986)A Multi-objective Perspective for Operator Scheduling using Fine-grained DVS Architecture, , , and . CoRR, (2013)Loop unrolling with fine grained power gating for runtime leakage power reduction., and . VDAT, page 1-6. IEEE, (2014)A New Technique for Runtime Leakage Reduction and Its Sensitivity and Parametric Yield Analysis Under Effective Channel-Length Variation., and . J. Low Power Electron., 6 (1): 80-92 (2010)