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Design of 4 × 4 MIMO-OFDMA receiver with precode codebook search for 3GPP-LTE.

, , , and . ISCAS, page 3957-3960. IEEE, (2010)

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Multi-stage lattice-reduction-aided MIMO detector using reverse-order LLL algorithm., , , and . APCCAS, page 100-103. IEEE, (2010)Power-Saving 4 ˟ 4 Lattice-Reduction Processor for MIMO Detection With Redundancy Checking., and . IEEE Trans. Circuits Syst. II Express Briefs, 58-II (2): 95-99 (2011)A constant-throughput LLL algorithm with deep insertion for LR-aided MIMO detection., , , and . ISCAS, page 1251-1254. IEEE, (2012)A 684Mbps 57mW joint QR decomposition and MIMO processor for 4×4 MIMO-OFDM systems., , , , and . A-SSCC, page 309-312. IEEE, (2011)Low-complexity lattice reduction architecture using interpolation-based QR decomposition for MIMO-OFDM systems., , , and . APCCAS, page 224-227. IEEE, (2012)Latency-constrained low-complexity lattice reduction for MIMO-OFDM systems., , , and . ICASSP, page 1677-1680. IEEE, (2011)Loop-Reduction LLL Algorithm and Architecture for Lattice-Reduction-Aided MIMO Detection., , and . J. Electr. Comput. Eng., (2012)A 6.4G LLR/s 8×8 64-QAM soft-output MIMO detector with lattice reduction preprocessing., , , and . VLSI-DAT, page 1-4. IEEE, (2017)A 576-Mbit/s 64-QAM 4 × 4 MIMO Precoding Processor With Lattice Reduction., , , and . IEEE Trans. Circuits Syst. II Express Briefs, 61-II (2): 95-99 (2014)Hardware-Efficient Interpolation-Based QR Decomposition and Lattice Reduction Processor for MIMO-OFDM Receivers., , and . J. Signal Process. Syst., 88 (3): 411-423 (2017)