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A 128Gb 1-bit/Cell 96-Word-Line-Layer 3D Flash Memory to Improve the Random Read Latency With tProg = 75 μs and tR = 4 μs., , , , , , , , , and 14 other author(s). IEEE J. Solid State Circuits, 56 (1): 225-234 (2021)A 1-Tb 4-b/cell 4-Plane 162-Layer 3-D Flash Memory With 2.4-Gb/s IO Interface., , , , , , , , , and 37 other author(s). IEEE J. Solid State Circuits, 58 (1): 316-328 (2023)A 1-Tb 4b/Cell 4-Plane 162-Layer 3D Flash Memory With a 2.4-Gb/s I/O Speed Interface., , , , , , , , , and 39 other author(s). ISSCC, page 130-132. IEEE, (2022)11.1 A 512Gb 3b/cell flash memory on 64-word-line-layer BiCS technology., , , , , , , , , and 47 other author(s). ISSCC, page 196-197. IEEE, (2017)13.5 A 128Gb 1b/Cell 96-Word-Line-Layer 3D Flash Memory to Improve Random Read Latency with tPROG=75µs and tR=4µs., , , , , , , , , and 13 other author(s). ISSCC, page 226-228. IEEE, (2020)30.4 A 1Tb 3b/Cell 3D-Flash Memory in a 170+ Word-Line-Layer Technology., , , , , , , , , and 49 other author(s). ISSCC, page 428-430. IEEE, (2021)