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Performance analysis and architecture evaluation of MPEG-4 video codec system.

, , , and . ISCAS, page 449-452. IEEE, (2000)

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Hardware-Efficient Architecture Design for Zerotree Coding in MPEG-4 Still Texture Coder., , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 86-A (2): 472-479 (2003)Scalable module-based architecture for MPEG-4 BMA motion estimation., , , and . ISCAS (2), page 245-248. IEEE, (2001)A novel cross-layer mesh router placement scheme for wireless mesh networks., , and . EURASIP J. Wireless Comm. and Networking, (2011)A Low Power 2-D DCT Chip Design Using Direct 2-D Algorithm., , , , and . ASP-DAC, page 145-150. IEEE, (1998)Design and implementation of JPEG encoder IP core., , , and . ASP-DAC, page 29-30. ACM, (2001)A Low Power 8 x 8 Direct 2-D DCT Chip Design., , , and . VLSI Signal Processing, 26 (3): 319-332 (2000)Hardware-efficient architecture design of tree-depth scanning and multiple quantization scheme for MPEG-4 still texture coding., , , and . ISCAS (2), page 193-196. IEEE, (2001)VLSI architecture design of MPEG-4 shape coding., , , , and . IEEE Trans. Circuits Syst. Video Techn., 12 (9): 741-751 (2002)Performance analysis and architecture evaluation of MPEG-4 video codec system., , , and . ISCAS, page 449-452. IEEE, (2000)A VLSI architecture design of VLC encoder for high data rate video/image coding., , , and . ISCAS (4), page 398-401. IEEE, (1999)