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Improve speed path identification with suspect path expressions., , , , , и . VLSI-DAT, стр. 1-4. IEEE, (2013)Diagnosing timing related cell internal defects for FinFET technology., , , , и . VLSI-DAT, стр. 1-4. IEEE, (2015)Differential Fault Simulation - a Fast Method Using Minimal Memory., и . DAC, стр. 424-428. ACM Press, (1989)Proofs: A Fast, Memory Efficient Sequential Circuit Fault Simulator., , и . DAC, стр. 535-540. IEEE Computer Society Press, (1990)A complete test set to diagnose scan chain failures., , и . ITC, стр. 1-10. IEEE Computer Society, (2007)Interconnect open defect diagnosis with minimal physical information., , , , , и . ITC, стр. 1-10. IEEE Computer Society, (2007)Improved volume diagnosis throughput using dynamic design partitioning., , , , , и . ITC, стр. 1-10. IEEE Computer Society, (2012)On Improving Diagnostic Test Generation for Scan Chain Failures., , , , и . Asian Test Symposium, стр. 41-46. IEEE Computer Society, (2009)On Using Design Partitioning to Reduce Diagnosis Memory Footprint., , , , и . Asian Test Symposium, стр. 219-225. IEEE Computer Society, (2011)Programmable Scan-Based Logic Built-In Self Test., , и . ATS, стр. 371-377. IEEE, (2007)