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Hand gesture recognition algorithm combining hand-type adaptive algorithm and effective-area ratio for efficient edge computing.

, , , , and . J. Electronic Imaging, (2021)

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An MTJ-Based Asynchronous System With Extremely Fine-Grained Voltage Scaling., , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 68 (1): 311-321 (2021)A High-Density and Reconfigurable SRAM-Based Digital Compute-In-Memory Macro for Low-Power AI Chips., , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 70 (9): 3589-3593 (September 2023)Hand gesture recognition algorithm combining hand-type adaptive algorithm and effective-area ratio for efficient edge computing., , , , and . J. Electronic Imaging, (2021)A scalable and reconfigurable 2.5D integrated multicore processor on silicon interposer., , , , , and . CICC, page 1-4. IEEE, (2015)A 2D mesh NoC with self-configurable and shared-FIFOs routers., , , , and . ASICON, page 1-4. IEEE, (2013)A fast multi-core virtual platform and its application on software development., , , , and . ASICON, page 1-4. IEEE, (2013)A 65nm 39GOPS/W 24-core processor with 11Tb/s/W packet-controlled circuit-switched double-layer network-on-chip and heterogeneous execution array., , , , , , , , , and 4 other author(s). ISSCC, page 56-57. IEEE, (2013)A low power register file with asynchronously controlled read-isolation and software-directed write-discarding., , , , and . ISCAS, page 349-352. IEEE, (2013)Enhancing aspect-based sentiment analysis with dependency-attention GCN and mutual assistance mechanism., , and . J. Intell. Inf. Syst., 62 (1): 163-189 (February 2024)NeuronLink: An Efficient Chip-to-Chip Interconnect for Large-Scale Neural Network Accelerators., , , , , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 28 (9): 1966-1978 (2020)