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Extended dynamic voltage scaling for low power design., , , и . SoCC, стр. 389-394. IEEE, (2004)CAS-FEST 2010: Mitigating Variability in Near-Threshold Computing., , , , , и . IEEE J. Emerg. Sel. Topics Circuits Syst., 1 (1): 42-49 (2011)Robust Clock Network Design Methodology for Ultra-Low Voltage Operations., , и . IEEE J. Emerg. Sel. Topics Circuits Syst., 1 (2): 120-130 (2011)24.3 A 36.8 2b-TOPS/W self-calibrating GPS accelerator implemented using analog calculation in 65nm LP CMOS., , , , , , , и . ISSCC, стр. 420-422. IEEE, (2016)14.7 A 288µW programmable deep-learning processor with 270KB on-chip weight storage using non-uniform memory hierarchy for mobile intelligence., , , , , , , , , и 4 other автор(ы). ISSCC, стр. 250-251. IEEE, (2017)Centip3De: a many-core prototype exploring 3D integration and near-threshold computing., , , , , , , , , и 5 other автор(ы). Commun. ACM, 56 (11): 97-104 (2013)Measurement techniques and interconnect estimation.. SLIP, стр. 79-81. ACM, (2000)Stress aware layout optimization., , , , и . ISPD, стр. 168-174. ACM, (2008)The great interconnect buffering debate: are you a chicken or an ostrich?, , , , и . ISPD, стр. 61. ACM, (2004)A 23mW face recognition accelerator in 40nm CMOS with mostly-read 5T memory., , , , , , , и . VLSIC, стр. 48-. IEEE, (2015)