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High performance architectures for Chip-to-Chip Communications on Network Line Cards.

, and . J. High Speed Networks, 16 (2): 193-209 (2007)

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3D-Mesh Interconnect Architecture for Network Processors., and . PDPTA, page 521-525. CSREA Press, (2005)Modelling and simulation of off-chip communication architectures for high-speed packet processors., , and . J. Syst. Softw., 79 (12): 1701-1714 (2006)Performance analysis of network protocol offload in a simulation environment., , and . ACM Southeast Regional Conference, page 762-763. ACM, (2006)Performance evaluation of wormhole routed network processor-memory interconnects., and . IPDPS, IEEE, (2006)Off-chip communication architectures for high throughput network processors., and . Comput. Commun., 32 (5): 867-879 (2009)Modelling and simulation of off-chip communication architectures for high-speed packet processors., , and . Circuits, Signals, and Systems, page 169-174. IASTED/ACTA Press, (2005)Performance evaluation of 3D-interconnect architectures for network line cards., and . Communications and Computer Networks, page 351-356. IASTED/ACTA Press, (2005)High performance architectures for Chip-to-Chip Communications on Network Line Cards., and . J. High Speed Networks, 16 (2): 193-209 (2007)Characterization of server performance bottlenecks in distributed interactive simulation environments., , and . Simul. Model. Pract. Theory, 16 (7): 746-753 (2008)A high throughput 3D-bus interconnect for network processors., and . Microprocess. Microsystems, 30 (1): 15-25 (2006)