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A 27% Active-Power-Reduced 40-nm CMOS Multimedia SoC With Adaptive Voltage Scaling Using Distributed Universal Delay Lines.

Y. Ikenaga, M. Nomura, S. Suenaga, H. Sonohara, Y. Horikoshi, T. Saito, Y. Ohdaira, Y. Nishio, T. Iwashita, M. Satou, K. Nishida, K. Nose, K. Noguchi, Y. Hayashi, and M. Mizuno. IEEE J. Solid State Circuits, 47 (4): 832-840 (2012)

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Yoshifumi Torisu

Mamiko Ikenaga

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A 27% Active-Power-Reduced 40-nm CMOS Multimedia SoC With Adaptive Voltage Scaling Using Distributed Universal Delay Lines.Y. Ikenaga, M. Nomura, S. Suenaga, H. Sonohara, Y. Horikoshi, T. Saito, Y. Ohdaira, Y. Nishio, T. Iwashita, M. Satou and 5 other author(s). IEEE J. Solid State Circuits, 47 (4): 832-840 (2012)A Circuit for Determining the Optimal Supply Voltage to Minimize Energy Consumption in LSI Circuit Operations.Y. Ikenaga, M. Nomura, Y. Nakazawa, and Y. Hagihara. IEEE J. Solid State Circuits, 43 (4): 911-918 (2008)Delay and power monitoring schemes for minimizing power consumption by means of supply and threshold voltage control in active and standby modes.M. Nomura, Y. Ikenaga, K. Takeda, Y. Nakazawa, Y. Aimoto, and Y. Hagihara. IEEE J. Solid State Circuits, 41 (4): 805-814 (2006)

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Disambiguation of "Ikenaga, Yoshifumi"

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A 27% Active-Power-Reduced 40-nm CMOS Multimedia SoC With Adaptive Voltage Scaling Using Distributed Universal Delay Lines.

Please choose a person to relate this publication to

Yoshifumi Torisu

Mamiko Ikenaga

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Ikenaga, Yoshifumi"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML A 27% Active-Power-Reduced 40-nm CMOS Multimedia SoC With Adaptive Voltage Scaling Using Distributed Universal Delay Lines.

Please choose a person to relate this publication to

Yoshifumi Torisu

Mamiko Ikenaga

Other publications of authors with the same name

Disambiguation

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URL
DOI
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Chicago
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A 27% Active-Power-Reduced 40-nm CMOS Multimedia SoC With Adaptive Voltage Scaling Using Distributed Universal Delay Lines.