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XDIVINSA: eXtended DIVersifying INStruction Agent to Mitigate Power Side-Channel Leakage.

, , , , and . ASAP, page 179-186. IEEE, (2021)

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The MareNostrum Experimental Exascale Platform (MEEP)., , , , , , and . Supercomput. Front. Innov., 8 (1): 62-81 (2021)Automated, inter-macro channel space adjustment and optimization for faster design closure., , and . SoCC, page 74-79. IEEE, (2017)Streaming FFT on REDEFINE-v2: an application-architecture design space exploration., , , , , , , and . CASES, page 127-136. ACM, (2009)Synthesis of application accelerators on Runtime Reconfigurable Hardware., , , , , , , and . ASAP, page 13-18. IEEE Computer Society, (2008)REDEFINE: Runtime reconfigurable polymorphic ASIC., , , , , , , , , and 1 other author(s). ACM Trans. Embed. Comput. Syst., 9 (2): 11:1-11:48 (2009)Symmetric $k$-Means for Deep Neural Network Compression and Hardware Acceleration on FPGAs., , , , and . IEEE J. Sel. Top. Signal Process., 14 (4): 737-749 (2020)Coyote: An Open Source Simulation Tool to Enable RISC- V in HPC., , and . DATE, page 130-135. IEEE, (2021)TAD: time side-channel attack defense of obfuscated source code., , and . ASP-DAC, page 58-63. ACM, (2019)Compiling Techniques for Coarse Grained Runtime Reconfigurable Architectures., , , , and . ARC, volume 5453 of Lecture Notes in Computer Science, page 204-215. Springer, (2009)Force-directed scheduling for Data Flow Graph mapping on Coarse-Grained Reconfigurable Architectures., , and . ReConFig, page 1-8. IEEE, (2014)