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13.2 A digital multimode polar transmitter supporting 40MHz LTE Carrier Aggregation in 28nm CMOS., , , , , , , , , and 13 other author(s). ISSCC, page 218-219. IEEE, (2017)A +32 dBm 1.85 GHz class-D outphasing RF PA in 130nm CMOS for WCDMA/LTE., , and . ESSCIRC, page 127-130. IEEE, (2011)A Nonlinear Switched State-Space Model for Capacitive RF DACs., , , , , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 64-I (6): 1342-1353 (2017)Phase Predistortion of a Class-D Outphasing RF Amplifier in 90 nm CMOS., , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 58-II (10): 642-646 (2011)A 16-dBm D-Band Power Amplifier with a Cascaded CE and CB Output Power Stage Using a Stub Matching Topology., , , , , , , , and . BCICTS, page 1-4. IEEE, (2019)A 39-GHz Frequency Tripler With >40-dBc Harmonic Rejection for 5G Communication Systems in 28-nm Bulk CMOS., , , , , , and . ESSCIRC, page 107-110. IEEE, (2019)Analysis of a 5.5-V Class-D Stage Used in +30-dBm Outphasing RF PAs in 130- and 65-nm CMOS., , and . IEEE Trans. Circuits Syst. II Express Briefs, 59-II (11): 726-730 (2012)A Class-D stage with harmonic suppression and DLL-based phase generation., , and . MWSCAS, page 45-48. IEEE, (2012)Least-Squares Phase Predistortion of a +30 dBm Class-D Outphasing RF PA in 65 nm CMOS., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 60-I (7): 1915-1928 (2013)Design and Analysis of a Class-D Stage With Harmonic Suppression., , and . IEEE Trans. Circuits Syst. I Regul. Pap., 59-I (6): 1178-1186 (2012)