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Injecting FPGA Configuration Faults in Parallel., and . FPT, page 198-205. IEEE, (2018)Accelerating Position-Aware Top-k ListNet for Ranking Under Custom Precision Regimes., , , , and . FPL, page 81-87. IEEE, (2019)System-level Linking of Synthesised Hardware and Compiled Software Using a Higher-order Type System., , , and . FPGA, page 214-217. ACM, (2015)Hardware Acceleration of Matrix Multiplication over Small Prime Finite Fields., and . ARC, volume 7806 of Lecture Notes in Computer Science, page 103-114. Springer, (2013)Termination detection for fine-grained message-passing architectures., , , , , , , , and . ASAP, page 17-24. IEEE, (2020)EASY: Efficient Arbiter SYnthesis from Multi-threaded Code., , , , and . FPGA, page 142-151. ACM, (2019)Heterogeneous Heartbeats: A framework for dynamic management of Autonomous SoCs., and . FPL, page 1-6. IEEE, (2014)PushPush: Seamless integration of hardware and software objects via function calls over AXI., , , , and . FPL, page 1-8. IEEE, (2015)Accelerating Top-k ListNet Training for Ranking Using FPGA., , , and . FPT, page 242-245. IEEE, (2018)StitchUp: automatic control flow protection for high level synthesis circuits., and . DAC, page 138:1-138:6. ACM, (2016)