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Fault-effect analysis on system-level hardware modeling using virtual prototypes., , , , and . FDL, page 1-7. IEEE, (2016)A model-based and simulation-assisted FMEDA approach for safety-relevant E/E systems., , , , and . DAC, page 1:1-1:6. ACM, (2015)Safety Evaluation of Automotive Electronics Using Virtual Prototypes: State of the Art and Research Challenges., , , , , , , , , and 15 other author(s). DAC, page 113:1-113:6. ACM, (2014)Speeding up safety verification by fault abstraction and simulation to transaction level., , , , and . VLSI-SoC, page 1-6. IEEE, (2016)Gate-Level-Accurate Fault-Effect Analysis at Virtual-Prototype Speed., , , , and . SAFECOMP Workshops, volume 9923 of Lecture Notes in Computer Science, page 144-156. Springer, (2016)Extending Verilator to Enable Fault Simulation., , , , , and . MBMV, page 1-6. VDE/IEEE, (2021)Transformation of Failure Propagation Models into Fault Trees for Safety Evaluation Purposes., , , , and . DSN Workshops, page 226-229. IEEE Computer Society, (2016)Efficient Checkpointing-Based Safety-Verification Flow Using Compiled-Code Simulation., , , , and . DSD, page 364-371. IEEE Computer Society, (2016)