Author of the publication

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Negative Capacitance Transistor to Address the Fundamental Limitations in Technology Scaling: Processor Performance.

H. Amrouch, G. Pahwa, A. Gaidhane, J. Henkel, and Y. Chauhan. IEEE Access, (2018)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Dhirendar Chauhan

Sangeeta Chauhan

Yogesh Rathi

Yogesh Bhargava

Babu Chauhan

Other publications of authors with the same name

Unified Model for Sub-Bandgap and Conventional Impact Ionization in RF SOI MOSFETs with Improved Simulator Convergence.C. Yadav, A. Dutta, S. Sirohi, E. Tamilmani, and Y. Chauhan. VLSID, page 328-333. IEEE Computer Society, (2016)Powering Disturb-Free Reconfigurable Computing and Tunable Analog Electronics with Dual-Port Ferroelectric FET.Z. Zhao, S. Deng, S. Chatterjee, Z. Jiang, M. Islam, Y. Xiao, Y. Xu, S. Meninger, M. Mohamed, R. Joshi and 8 other author(s). CoRR, (2023)Improved modeling of flicker noise including velocity saturation effect in FinFETs and experimental validation.R. Goel, W. Wang, and Y. Chauhan. Microelectron. J., (2021)Modeling STI Edge Parasitic Current for Accurate Circuit Simulations.S. Khandelwal, H. Agarwal, J. Duarte, K. Chan, S. Dey, Y. Chauhan, and C. Hu. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 34 (8): 1291-1294 (2015)Performance, Power and Cooling Trade-Offs with NCFET-based Many-Cores.M. Rapp, S. Salamin, H. Amrouch, G. Pahwa, Y. Chauhan, and J. Henkel. DAC, page 41. ACM, (2019)BSIM - Industry standard compact MOSFET models.Y. Chauhan, S. Venugopalan, M. Karim, S. Khandelwal, N. Paydavosi, P. Thakur, A. Niknejad, and C. Hu. ESSCIRC, page 30-33. IEEE, (2012)NCFET to Rescue Technology Scaling: Opportunities and Challenges.H. Amrouch, V. van Santen, G. Pahwa, Y. Chauhan, and J. Henkel. ASP-DAC, page 637-644. IEEE, (2020)BSIM-BULK: Accurate Compact Model for Analog and RF Circuit Design.C. Gupta, R. Goel, H. Agarwal, C. Hu, and Y. Chauhan. CICC, page 1-8. IEEE, (2019)Suspended-gate FET as a sleep transistor for ultra-low stand-by power applications.D. Tsamados, Y. Chauhan, C. Eggimann, and A. Ionescu. Nano-Net, page 8. ICST/ACM, (2007)Power Side-Channel Attacks in Negative Capacitance Transistor.J. Knechtel, S. Patnaik, M. Nabeel, M. Ashraf, Y. Chauhan, J. Henkel, O. Sinanoglu, and H. Amrouch. IEEE Micro, 40 (6): 74-84 (2020)

BibSonomy

Disambiguation of "Chauhan, Yogesh Singh"

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Negative Capacitance Transistor to Address the Fundamental Limitations in Technology Scaling: Processor Performance.

Please choose a person to relate this publication to

Dhirendar Chauhan

Sangeeta Chauhan

Yogesh Rathi

Yogesh Bhargava

Babu Chauhan

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Chauhan, Yogesh Singh"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Negative Capacitance Transistor to Address the Fundamental Limitations in Technology Scaling: Processor Performance.

Please choose a person to relate this publication to

Dhirendar Chauhan

Sangeeta Chauhan

Yogesh Rathi

Yogesh Bhargava

Babu Chauhan

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Negative Capacitance Transistor to Address the Fundamental Limitations in Technology Scaling: Processor Performance.