Author of the publication

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

Runtime-assisted cache coherence deactivation in task parallel programs., , , , and . SC, page 35:1-35:12. IEEE / ACM, (2018)Initial Evaluation of Multimedia Extensions on VLIW Architectures., and . SAMOS, volume 3133 of Lecture Notes in Computer Science, page 403-412. Springer, (2004)Performance and Power Evaluation of Clustered VLIW Processors with Wide Functional Units., , , , and . SAMOS, volume 3133 of Lecture Notes in Computer Science, page 88-97. Springer, (2004)Bandwidth of Crossbar and Multiple-Bus Connections for Multiprocessors., , and . IEEE Trans. Computers, 31 (12): 1227-1234 (1982)Speculative early register release., , , and . Conf. Computing Frontiers, page 291-302. ACM, (2006)Breaking the bandwidth wall in chip multiprocessors., , , and . ICSAMOS, page 255-262. IEEE, (2011)Access to streams in multiprocessor systems., , and . PDP, page 310-316. IEEE, (1993)Novel SRAM bias control circuits for a low power L1 data cache., , , , and . NORCHIP, page 1-6. IEEE, (2012)A performance evaluation of the multiple bus network for multiprocessor systems., , , , and . SIGMETRICS, page 200-206. ACM, (1983)Dynamic Tolerance Region Computing for Multimedia., , and . IEEE Trans. Computers, 61 (5): 650-665 (2012)