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Disambiguation of "Pasupureddi, Vijaya Sankara Rao"

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Current-mode echo cancellation for full-duplex chip-to-chip data communication.

, and . APCCAS, page 748-751. IEEE, (2010)

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Tanigopula Siva Sankara Rao

Vijaya Shukla

Sankara Kunjakruishna Pillai

Nidamboor Vasanth Rao

Boloor Ramananda Rao

 

Other publications of authors with the same name

Charge controlled delay element enabled widely linear power efficient MPCG-MDLL in 1.2V, 65nm CMOS., and . I. J. Circuit Theory and Applications, 48 (2): 198-213 (2020)A power-efficient current-integrating hybrid for full-duplex communication over chip-to-chip interconnects., and . Int. J. Circuit Theory Appl., 50 (12): 4219-4233 (December 2022)Active-terminated transmitter and receiver circuits for high-speed low-swing duobinary signaling., and . Int. J. Circuit Theory Appl., 40 (4): 355-376 (2012)Power Efficient Echo-Cancellation Based Hybrid for Full-Duplex Chip-to-Chip Interconnects., , and . ISCAS, page 852-856. IEEE, (2022)A Low Power CMOS Imager Based on Distributed Compressed Sensing., and . VLSID, page 534-538. IEEE Computer Society, (2014)RT-MIL-STD-1553+: Remote terminal controller for MIL-STD-1553B at 100-Mb/s data rate., and . ISQED, page 502-506. IEEE, (2015)Residue monitor enabled charge-mode adaptive echo-cancellation for simultaneous bidirectional signaling over on-chip interconnects., , and . Microelectron. J., (2020)A Power Efficient Fully Differential Back Terminated Current-Mode HDMI Source., , and . VLSID, page 575-579. IEEE Computer Society, (2014)Design and simulation of a wideband channelized transceiver for DRFM applications., , and . APCCAS, page 635-638. IEEE, (2014)A New Double Data Rate(DDR) Dual-Mode Duobinary Transmitter Architecture., , and . VLSI Design, page 12-17. IEEE Computer Society, (2011)